A forty-five-year strategic partnership across PCs, cloud, AI, and the next generation of silicon.
A five-year extension of the IBM-Lam partnership turns the next generation of High-NA EUV lithography into a coordinated bet — and pulls the next generation of silicon, the kind Intel and the broader ecosystem need, forward by years rather than months.
On 10 March 2026, IBM and Lam Research announced a five-year extension of their long-running collaboration on sub-1nm logic and High-NA EUV lithography. For the broader semiconductor ecosystem — including Intel, which has been a co-developer at Albany NanoTech for years — it's the most concrete signal yet that the post-2nm roadmap is no longer hypothetical.
The IBM-Lam relationship goes back more than ten years and threads through some of the most consequential silicon milestones of the period — including nanosheet device architecture and the world's first 2nm node chip, which IBM unveiled in 2021. The new arrangement extends that work into the regime that comes after 2nm: sub-1nm scaling, where the geometry, materials, and lithography have to be co-designed as one system.
It is also where High-NA EUV lithography becomes essential. High-NA — short for high numerical aperture — is the next generation of extreme ultraviolet exposure, capable of resolving feature sizes that current EUV cannot. IBM and Lam are committing to drive the dry-resist and process breakthroughs that High-NA will require in production.
"Lam has been a critical partner to IBM for over a decade, contributing to key breakthroughs in logic scaling and device architecture such as nanosheet and the world's first 2nm node chip. We are thrilled to be expanding our collaboration to tackle the next set of challenges to enable High-NA EUV lithography and sub-1nm nodes."
Intel is a longtime collaborator at the NY CREATES Albany NanoTech Complex — the physical home of much of this work. The High-NA EUV Center being stood up there is positioned, as IBM Chairman and CEO Arvind Krishna noted in the related $10 billion New York chip-partnership announcement, as the spine of a U.S. semiconductor pipeline that has to keep up with manufacturing demand for technologies like generative AI.
For Intel specifically, the practical consequence is that Foundry-scale manufacturing of sub-1nm nodes — the kind of technology required to keep pace with the AI workload curve — has a credible industrial path. Not a single company's roadmap. An ecosystem coordinating around shared infrastructure and shared milestones.
"As the industry enters a new era of 3D scaling, progress depends on rethinking how materials, processes, and lithography come together as a single, high-density system. We are proud to build on our successful collaboration with IBM to drive High-NA EUV dry resist and process breakthroughs, accelerating the development of lower power and higher performance transistors that will be critical for AI era."
Read together with the May 2024 Gaudi 3 announcement on IBM Cloud, the December 2023 $10B New York chip partnership, and the 2022 positioning of Albany as the model the CHIPS Act is trying to scale, the through-line is unmistakable: a multi-year, multi-company plan to keep frontier silicon in motion — with IBM, Intel, and a small number of partners doing the work in coordinated public.
For Intel, the value is not just in the technology that comes out of Albany. It is in the credibility of being publicly partnered with the institutions writing the next chapter of silicon — at the same time it is partnered with IBM Cloud and watsonx for the AI infrastructure layer that runs on top of that silicon. The two pieces are the same story.